The present invention relates to the manufacturing of integrated circuits. More specifically, the present invention relates to identifying defects in integrated circuits being manufactured on a wafer.
Integrated circuits are commonly manufactured in batches on wafers. Multiple integrated circuits are manufactured on a single silicon wafer during the manufacturing process. Referring now to FIG. 1, there is shown a silicon wafer having a plurality of integrated circuits disposed thereon referenced by numbers 12, 14, 16, and 18.
During the manufacturing process, multiple masking processes are performed on the semiconductor wafer. Each masking process defines where features on various layers that make up the integrated circuit are to be positioned. For example, a layer of polycrystalline silicon may be deposited on a wafer. Then photosensitive resist is coated on the wafer and selectively exposed to light so that after developing the resist, the remaining resist forms a pattern. This pattern is then transferred to the polysilicon during an etch step so that after the remaining resist is removed, the polycrystalline silicon forms a pattern defined by the selective light exposure.
This masking and etching process sequence is repeatedly carried out on each wafer to create the intricate interconnected patterns of semiconductors, insulators, and metals needed to create the desired integrated circuit (IC).
The process described above is carried out to produce a plurality of IC""s on a wafer as shown in FIG. 1. For example, a single silicon wafer may be the basis for tens to thousands of IC""s. The ability to manufacture a plurality of IC""s on a single silicon wafer reduces the overall cost of production, thereby passing these cost savings onto the consumer in the form of inexpensive IC""s.
With advancements in technology, IC""s have become very small and very complex. With each generation, IC features become smaller because of advancements in the manufacturing process described above. However, with these advancements it has become more difficult to detect defects.
As part of the manufacturing process, in an effort to reduce the number of defective IC dice, it is common to inspect all of, or a sample of, the dice on a sampling of the wafers being produced. The inspection may be an optical inspection with very sensitive optical instruments capable of detecting defects of the size of a minimum feature of the IC or might be an electrical test that, in the case of memories, is capable of locating the position of an electrical defect to within the area of one small cell. The artifacts that are detected serve to guide the engineers to where defects, which may lead to yield loss, occur.
Referring now to FIG. 1 there is shown a wafer having four dice labeled 12, 14, 16, and 18. The labeled dice illustrate how a wafer may be inspected during manufacturing. For example, each of these dice, either picked randomly or according to some reason, would be inspected for defects.
Referring now to FIG. 2, there is shown a hypothetical collection of defects that might be observed in an inspection report generated from inspecting the dice shown in FIG. 1. A line defect is illustrated on die 12 in FIG. 2. A line defect may be caused by a scratch on the wafer. Also shown on dice 12, 14, and 16 in FIG. 2, are a plurality of xe2x80x9cpointxe2x80x9d defects 22, 26, 28, 34, 36, and 38. Also illustrated on die 11 in FIG. 2 is a large continuous defect 30 and a cluster of point defects 32.
Referring now to prior art FIG. 3, there are shown defects 42 through 68 that might be observed on another inspection report of the same dice later in the manufacturing process. The outline of the die is shown for illustrative purposes only in FIGS. 2 and 3 and would not be generally available in a standard defect inspection report.
Defects that occur on one layer may propagate through and also appear on subsequent levels during the manufacturing and inspection process. For example, a large contaminating particle that remains after cleaning of the polysilicon layer, might penetrate through the intervening dielectric layer and be seen on the metal contact layer. It is important to identify these propagating defects so that the cause of the defects can be correctly assigned.
After locating the defects, an overlay report may be generated in which the defects from the inspections of the successive layers are displayed together with the intention of identifying those defects that are reported to be at the same location on inspection of successive layers. However, experience has shown that there is an offset in the reported origin of the inspections between layers.
Referring now to FIG. 4, there is shown an exemplary overlay report as would be created after performing at least two inspections. As shown in FIG. 4, an offset in the origins of the coordinate systems used to report the location of the defects may cause the defects from one layer to-be incorrectly positioned with respect to those defects of a second layer. This offset has been a recurring problem in the manufacture of integrated circuits and, as the size of the integrated circuits features are reduced and the number of dice on a wafer increases, there is a growing need to correct this problem.
Thus, when an overlay inspection report is generated as shown in FIG. 4, propagating defects may not be identified. As shown in FIG. 4, only individual point defects from the defect clusters 32 and 62 would be selected. An attempt to identify correlated defects as those lying within some critical distance of each other would mistakenly select the pair of defects 48, both of which come from the second inspection. A more sophisticated correlation algorithm based on defects from successive inspections that lie within a critical distance would misidentify defects 45 and 26 as being correlated when in fact they are not.
Therefore, there is a need for a procedure for automatically detecting the origin offset between the inspections and correcting the offset in the overlay report so that the correlated defects that propagate between layers can be identified correctly. The present invention provides a method and apparatus for correcting these.
The present invention is directed towards a method for determining the offset between at least two origins of a coordinate system used for at least two different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of the at least two origins based on the said selected pairs of said data sets.
The present invention is also directed towards a method for determining the offset between at least three origins of a coordinate system used for at least three different defect inspections of a wafer with integrated circuits disposed on it. An embodiment of the method comprises: finding all possible pairwise links between layers; constructing a tree of links; identifying all indirect paths along which layers can be linked; calculating statistics of offsets between indirectly linked layers; determining whether any pair of layers are linked by multiple paths; listing each pair of layers linked by multiple paths, if there are any pair of layers linked by multiple paths; selecting a listed pair of layers that have not been previously selected; determining whether offsets associated with said listed pair of layers are within confidence limits of each other; selecting the best estimate of said offsets; determining whether the system has selected all the of the listed pairs; and selecting a listed pair of layers that have not been previously selected.
The invention further relates to machine readable media on which are stored embodiments of the present invention. It is contemplated that any media suitable for retrieving instructions is within the scope of the present invention. By way of example, such media may take the form of magnetic, optical, or semiconductor media. The invention also relates to data structures that contain embodiments of the present invention, and to the transmission of data structures containing embodiments of the present invention.